The present invention relates to a dynamic circuit, and more particularly to a technology for reducing the number of stacks of transistors constituting a dynamic circuit.
In currently available semiconductor integrated circuits, static circuits mainly represented by complementary metal oxide semiconductor (CMOS) circuits are widely used. In CMOS circuits, the output remains unchanged unless the input changes, and the current consumption is only caused by a minute leak component and an active component occurring at value transition. Thus, CMOS circuits have an advantage that the consumed current is comparatively small. As a drawback of CMOS circuits, the power delay product is comparatively large when high-speed operation is performed.
In general, a CMOS circuit has individual circuits for executing logic operation of a function of which implementation is desired, that is, an evaluation function ƒ and its complementary function ƒ*. The functions ƒ and ƒ* are generally composed of NMOS transistors and PMOS transistors, respectively, and signals generated from the respective functions propagate to functions in the next stage, to implement circuit operation. Thus, in CMOS circuits, in which double circuits are formed for one function, the circuit scale and the signal input load are comparatively large. In particular, since PMOS transistors must have a transistor size about twice as large as NMOS transistors because of the difference in carrier mobility therebetween, the increase of the input load will be significant. This problem is not specific to CMOS circuits, but is common to static circuits as a whole including differential cascode voltage switch logic (DCVSL) and the like.
Dynamic circuits are known as having a circuit structure supplementing the drawback of the static circuits (see U.S. Pat. No. 5,532,625 (FIG. 3A), for example). In general, in dynamic circuits, a phase of initializing the output with an initialization function g and a phase of evaluating the input with a function of which implementation is desired, that is, an evaluation function ƒ operate in a time-division manner. The operations with the evaluation function ƒ and the initialization function g are respectively called evaluation operation and precharge operation. Signals are generated and propagate with the evaluation operation, and functions in the next stage perform the precharge operation and the evaluation operation, to thereby implement circuit operation. In this way, in dynamic circuits, in which only addition of an initialization function is necessary for one function, the circuit scale and the signal input load can be comparatively small. In particular, since the initialization operation is performed using a clock signal, the input load is dependent only on the evaluation function ƒ and thus is reduced to about a third of that of CMOS circuits.
To allow low-voltage operation of a dynamic circuit, it is necessary to reduce the threshold voltage of respective transistors constituting the dynamic circuit. For low leakage, however, the threshold voltage should preferably be high. Thus, since low-voltage operation and low leakage are requirements contradicting to each other, reduction in the number of stages of transistors connected in series is a requisite to attain both requirements. For this reason, with the process miniaturization, it has become difficult to implement multi-stack logic (evaluation circuit) in dynamic circuits. Also, because of occurrence of a leak, in particular, it has become very difficult to design a keeper circuit that holds the voltage of a dynamic node. To solve this problem, in some techniques, an evaluation control transistor that will otherwise be connected in series with an evaluation circuit is omitted to reduce the number of stacks, and precharge of a dynamic node is pulse-controlled to prevent unintentional flow of a through current (see U.S. Pat. No. 5,825,208 (FIG. 5), for example).
In the cases that two or more stacks exist and that an evaluation control transistor exists, noise may possibly occur with charge sharing. In particular, charge sharing is likely to occur in a domino circuit in which multiple stacks are provided to implement AND logic. Conventionally, charge sharing is suppressed by providing a circuit that supplies charge to a dynamic node (see U.S. Pat. No. 5,483,181 (FIG. 3), for example).
Dynamic circuits operate based on single-direction transition. Therefore, in a domino circuit composed of multi-staged connection of such dynamic circuits, negative logic cannot be handled in a simple way. As techniques of handling negative logic with a domino circuit, disclosed are a dual logic structure in which negative logic is produced as being in the logic duality relationship with positive logic (see U.S. Pat. No. 5,389,835 (FIG. 1), for example) and an inverted logic structure in which negative logic is produced forcefully by inverting the output of a dynamic circuit (see U.S. Pat. No. 5,402,012 (FIG. 1), for example).
As described above, the number of stacks increases with the existence of an evaluation control transistor and this is likely to cause charge sharing. The technology for reducing charge sharing described above will raise another problem of increasing the circuit scale.
The provision of an evaluation control transistor also causes a problem as follows, in addition to the increase in the number of stacks. Assuming an evaluation circuit composed of transistors connected in parallel, for example, if one of the transistors is ON, a capacitance formed between this transistor and an evaluation control transistor will be added redundantly as a parasitic capacitance of a dynamic node, causing a redundant current to flow during precharge operation and during evaluation operation.
In the technique of performing pulse-controlled precharge for the purpose of omitting the evaluation control transistor, it is necessary to secure the pulse width responsive to the operation conditions and the capacitance of the dynamic node. In particular, when the pulse width is to be secured using a delay buffer, a margin of a sufficiently large delay amount must be given to ensure precharge even in the worst conditions. This will however increase the overhead of the circuit.
The time required from start of precharge until the voltage of a dynamic node reaches a predetermined level depends on the drive capability of a precharge circuit and the capacitance of the dynamic node. More specifically, precharge will be completed comparatively fast if the drive capability of the precharge circuit is high or the capacitance of the dynamic node is small, while the time required until completion of precharge will be comparatively long if the drive capability of the precharge circuit is low or the capacitance of the dynamic node is large. In general, the capacitance of a dynamic node varies because the dynamic node has a parasitic capacitance typified by a wiring capacitance and a transistor source-drain capacitance. Also, the drive capability of a precharge circuit varies. In view of this, it is difficult to determine an optimal pulse width in the pulse-controlled precharge. With an unnecessarily long pulse width, a through current will flow if a logic condition is satisfied during the precharge.
In the handling of negative logic in a domino circuit described above, in the case of the dual logic structure, in which both positive logic and negative logic are implemented with single-direction transition-based signals, no erroneous operation will occur even if precharge is started prior to finalization of an input signal. In other words, in the dual logic structure, the circuit operates based on the evaluation operation, and thus the constraint between the timing of start of precharge and the timing of finalization of an input signal is comparatively relaxed. However, the dual logic structure has the following drawbacks.
The circuit scale will increase because it is necessary to provide two evaluation circuits that are in the logic duality relationship with each other. Also, one of the two evaluation circuits will be AND logic without fail, requiring serial connection of a plurality of transistors. In the dual logic structure, therefore, the problem of multiple stacks is left unsolved. For example, in implementation of 5-input OR logic, 5-input AND logic will be necessary as the dual logic thereof. In particular, if the number of stacks is limited by the circuit structure, it will be difficult to configure multi-input AND logic.
Meanwhile, in the case of the inverted logic structure, in which negative logic is obtained simply by inverting the output of a dynamic circuit, the problem of increasing the circuit scale is solved. However, to guarantee the dual-direction transition-based operation, it must be ensured that precharge should be completed prior to finalization of the input signal. To attain this, an evaluation control transistor is a requisite. Thus, in the inverted logic structure, the constraint between the timing of start of precharge and the timing of finalization of an input signal is very strict. More specifically, the time allocatable to setups and logic propagation will be the remainder left after subtracting a clock skew margin from the period of a clock signal for precharge control. In other words, the logic propagation time allowed in one cycle will be reduced due to a clock skew. In particular, in high-frequency operation, in which while the clock period becomes short, it is still difficult to reduce the clock skew, high-speed implementation will be difficult. Also, serial connection of transistors will still be required to implement multi-input AND logic, and thus the problem of multiple stacks is yet to be solved.